EXTRA Exploiting eXascale Technology with Reconfigurable Architectures
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Publications

    2018
    1. R. Zhao, H. Ng, W. Luk and X. Niu, "Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA" in 28th International Conference on Field Programmable Logic and Applications (FPL), 2018.
    2. A. Cross, L. Guo, W. Luk and M. Salmon, "CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems" in 28th International Conference on Field Programmable Logic and Applications (FPL), 2018.
    3. R. Zhao, S. Liu, H. Ng, E. Wang, J. J. Davis, X. Niu, X. Wang, H. Shi, G. A. Constantinides, P. Y. Cheung and others, "Hardware Compilation of Deep Neural Networks: An Overview" in IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018.
    4. S. Shao, J. Tsai, M. Mysior, W. Luk, T. Chau, A. Warren and B. Jeppesen, "Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control" in IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018.
    5. F. P. Russell, J. S. Targett and W. Luk, "From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations" in IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018.
    6. H. Ng, S. Liu and W. Luk, "ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development" in Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018, pp. 189--198.
    7. A. Funie, P. Grigoras, P. Burovskiy, W. Luk and M. Salmon, "Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies" in Journal of Signal Processing Systems, 2018, pp. 39--52.
    8. S. Liang, S. Yin, L. Liu, W. Luk and S. Wei, "FP-BNN: Binarized neural network on FPGA" in Neurocomputing, 2018, pp. 1072--1086.
    2017
    1. E. Hung, T. Todman and W. Luk, "Transparent In-Circuit Assertions for FPGAs" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, pp. 1-1.
    2. M. Bacis, G. Natale, E. Del Sozzo and M. D. Santambrogio, "A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA" in 2017 IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW) - RAW, June 2017.
    3. J. Arram, T. Kaplan, W. Luk and P. Jiang, "Leveraging FPGAs for Accelerating Short Read Alignment" in IEEE/ACM Transactions on Computational Biology and Bioinformatics, May 2017, pp. 668-677.
    4. L. Gan, H. Fu, O. Mencer, W. Luk and G. Yang, "Chapter Four - Data Flow Computing in Geoscience Applications" in Advances in Computers, 2017, pp. 125--158.
    5. M. Rabozzi, G. Natale, E. Del Sozzo, A. Scolari, L. Stornaiuolo and M. Santambrogio, "Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project" in 2017 Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2017, pp. 410--415.
    6. T. Becker, P. Burovskiy, A. M. Nestorov, H. Palikareva, E. Reggiani and G. Gaydadjiev, "From exaflop to exaflow" in Design, Automation Test in Europe Conference Exhibition (DATE), 2017, March 2017, pp. 404-409.
    7. A. Kulkarni, A. Werner, F. Fricke, D. Stroobandt and M. Huebner, "Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications" in 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017), Monterey, CA, USA, Feb. 22, 2017, 2017.
    8. G. Inggs, D. B. Thomas and W. Luk, "A Domain Specific Approach to High Performance Heterogeneous Computing" in IEEE Transactions on Parallel and Distributed Systems, Jan 2017, pp. 2-15.
    2016
    1. W. Zhao, H. Fu, W. Luk, T. Yu, S. Wang, B. Feng, Y. Ma and G. Yang, "F-CNN: An FPGA-based framework for training Convolutional Neural Networks" in 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2016, pp. 107-114.
    2. G. Guidi, L. Di Tucci and M. D. Santambrogio, "ProFAX: A hardware acceleration of a protein folding algorithm" in Research and Technologies for Society and Industry Leveraging a better tomorrow (RTSI), 2016 IEEE 2nd International Forum on, 2016, pp. 1--6.
    3. A. Kulkarni and D. Stroobandt, "MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization" in Design Automation for Embedded Systems, 2016, pp. 1--19.
    4. M. Arnaboldi, M. Ferroni and M. D. Santambrogio, "Towards a Performance-Aware Power Capping Orchestrator for the Xen Hypervisor" in EWiLi, 2016.
    5. C. Kritikakis, G. Chrysos, A. Dollas and D. N. Pnevmatikatos, "An FPGA-based High-Throughput Stream Join Architecture" in 26th International Conference on Field-Programmable Logic and Applications (FPL), 2016.
    6. D. Vercruyce, E. Vansteenkiste and D. Stroobandt, "Runtime-quality tradeoff in partitioning based multithreaded packing" in 2016 26th International Conference on Field Programmable Logic and Applications (FPL), Aug 2016, pp. 1-9.
    7. P. Grigoraş, P. Burovskiy, W. Luk and S. Sherwin, "Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA" in 2016 26th International Conference on Field Programmable Logic and Applications (FPL), Aug 2016, pp. 1-9.
    8. X. Niu, N. Ng, T. Yuki, S. Wang, N. Yoshida and W. Luk, "EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits" in 2016 26th International Conference on Field Programmable Logic and Applications (FPL), Aug 2016, pp. 1-4.
    9. H. Zhou, X. Niu, J. Yuan, L. Wang and W. Luk, "Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules" in 2016 26th International Conference on Field Programmable Logic and Applications (FPL), Aug 2016, pp. 1-8.
    10. P. Bahrebar and D. Stroobandt, "Online reconfigurable routing method for handling link failures in NoC-based MPSoCs" in 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), June 2016, pp. 1-8.
    11. B. Lindsey, M. Leslie and W. Luk, "A Domain Specific Language for accelerated Multilevel Monte Carlo simulations" in 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2016, pp. 99-106.
    12. D. Stroobandt, A. L. Varbanescu, C. B. Ciobanu, M. Al Kadi, A. Brokalakis, G. Charitopoulos, T. Todman, X. Niu, D. Pnevmatikatos, A. Kulkarni, E. Vansteenkiste, W. Luk, M. D. Santambrogio, D. Sciuto, M. Huebner, T. Becker, G. Gaydadjiev, A. Nikitakis and A. J. Thom, "EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures" in Reconfigurable Communication-centric Systems-on-Chip, 2016, pp. 1--7.
    13. G. Natale, G. Stramondo, R. Cattaneo, P. Bressana, D. Sciuto and M. D. Santambrogio, "A Polyhedral Model-based Framework for Dataflow Implementation on FPGA devices of Iterative Stencil Loops" in International Conference On Computer Aided Design (ICCAD), 2016.
    14. J. M. P. Cardoso, J. G. F. Coutinho, T. Carvalho, P. C. Diniz, Z. Petrov, W. Luk and F. Gonçalves, "Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach" in Software: Practice and Experience, 2016, pp. 251--287.
    15. A. Solazzo, E. Del Sozzo, I. De Rose, M. De Silvestri, G. C. Durelli and M. D. Santambrogio, "Hardware Design Automation of Convolutional Neural Networks" in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI‘16), July 2016, pp. To Appear.
    16. M. Rabozzi, G. C. Durelli, A. Miele, J. Lillis and M. D. Santambrogio, "Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, pp. 1-14.
    17. A. Kourfali and D. Stroobandt, "Efficient hardware debugging using parameterized FPGA reconfiguration" in 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016, pp. 277--282.
    18. A. Kulkarni, E. Vansteenkiste, D. Stroobandt, A. Brokalakis and A. Nikitakis, "A fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing applications" in 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016, pp. 265-270.
    19. E. Del Sozzo, A. Solazzo, A. Miele and M. D. Santambrogio, "On the Automation of High Level Synthesis of Convolutional Neural Networks" in 2016 IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW) - RAW, May 2016, pp. To Appear.
    20. M. El-Hadedy, H. Mihajloska, D. Gligoroski, A. Kulkarni, D. Stroobandt and K. Skadron, "A 16-Bit Reconfigurable Encryption Processor for p-Cipher" in 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), May 2016, pp. 162-171.
    21. M. Kurek, M. P. Deisenroth, W. Luk and T. Todman, "Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs" in 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2016, pp. 84-87.
    22. A. Kulkarni and D. Stroobandt, "How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization" in International Journal of Reconfigurable Computing, 2016, pp. 12.
    23. S. Wang, X. Niu, N. Ma, W. Luk, P. Leong and Y. Peng, "A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification", 2016, pp. 105--116.
    24. P. Grigoras, P. Burovskiy and W. Luk, "CASK: Open-Source Custom Architectures for Sparse Kernels" in Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016, pp. 179--184.
    25. R. Cattaneo, G. Natale, C. Sicignano, D. Sciuto and M. D. Santambrogio, "On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach" in ACM Trans. Archit. Code Optim., December 2015, pp. 53:1--53:26.
    26. K. Cheung, S. R. Schultz and W. Luk, "NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors" in Frontiers in Neuroscience, 2016, pp. 516.
    2015
    1. A. Kulkarni, V. Kizheppatt and D. Stroobandt, "MiCAP: A custom Reconfiguration Controller for Dynamic Circuit Specialization" in ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on, Dec 2015, pp. 1-6.
    2. P. Bahrebar and D. Stroobandt, "Design and exploration of routing methods for NoC-based multicore systems" in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Dec 2015, pp. 1-4.
    3. C. B. Ciobanu, A. L. Varbanescu, D. Pnevmatikatos, G. Charitopoulos, X. Niu, W. Luk, M. D. Santambrogio, D. Sciuto, M. A. Kadi, M. Huebner, T. Becker, G. Gaydadjiev, A. Brokalakis, A. Nikitakis, A. J. W. Thom, E. Vansteenkiste and D. Stroobandt, "EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing" in Proceedings of the 18th International Conference on Computational Science and Engineering (CSE 2015), October 2015, pp. 339-342.
    © 2015-2024 EXTRA

    The EXTRA project has received funding from the European Union Horizon 2020 Framework Programme (H2020-EU.1.2.2.) under grant agreement number 671653.