Mont-Blanc: European Approach Towards Energy Efficient High Performance
Mont-Blanc develops HPC solutions starting from commodity mobile processors. The goal of the project is developing an exascale platform featuring a cluster of commodity mobile processors. In this case the goals will be the same as those of EXTRA in terms of the realization of exascale computing solutions. EXTRA differs from Mont-Blanc by the fact that in EXTRA we will exploit highly customized hardware to ensure performance; this change of target solution will most likely ensure to EXTRA an advantage in terms of energy consumption which in a large scale cluster for HPC computation is the key point that prevents the current technology to reach the exascale target.
ANTAREX: AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems
To reach Exascale computing (1018 FLOPs), current supercomputers must achieve an energy efficiency “quantum leap” that allows this level of computation to be done at around 20 Megawatts. This will only be possible if we can target all layers of the system, from the software stack to the cooling system.
ANTAREX proposes a holistic approach capable of controlling all the decision layers in order to implement a self-adaptive application optimized for energy efficiency.
How to Get There?
- Introduce a new DSL for expressing adaptivity and autotuning strategies
- Enable performance and energy control capabilities using software knobs
- Design control-loops capable of operating each application at the maximum energy-efficient and thermally-safe point
SAVE: Self-Adaptive Virtualization-Aware High-Performance / Low-Energy Heterogeneous System Architectures
SAVE aims at developing technology for managing heterogeneous system architectures composed of CPUs, GPUs and FPGA to optimize performance per energy tradeoffs in HPC and embedded system scenarios. While not focusing explicitly on reconfiguration, one of the scenarios where SAVE is working is the development of technologies for improving performance per energy trade-off using FPGA devices in an HPC scenario. EXTRA will fit in this context, developing new technologies and applications that can be combined in this new view of heterogeneous HPC systems, but with a clear focus on run-time reconfiguration.
EUROSERVER: Green Computing Node for European micro-servers
EUROSERVER targets the design of power-efficient data centres. EUROSERVER addresses the challenges of efficient data servers in a holistic manner, using low power ARM processors in a system architecture using 3D integration, assuring good scalability in terms of number of cores, memory and I/O. The power efficient techniques developed in the FP7 project EUROSERVER are also applicable to EXTRA. However, EXTRA focuses on HPC workloads and specifically targets reconfigurable architectures. Avoiding I/O and memory bottlenecks is crucial for exascale computing, and in EXTRA the research will also consider these limitations from the perspective of the systems utilizing reconfigurable accelerators.
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
FASTER adopts a holistic approach for supporting a complete methodology that allows designers to easily implement and verify a system specification on a platform that includes one or more general purpose processor(s) combined with multiple acceleration modules implemented on one or multiple reconfigurable devices. FASTER includes reconfigurability as an explicit design concept in computing systems design and the results will be the basis for much of the EXTRA research. FASTER focused mainly on providing methods and tools for including run-time reconfiguration in every aspect of the design methodology for commercial FPGA devices. In EXTRA, we will combine this with novel reconfigurable architecture models to develop a platform addressing both the architecture and the tools for reconfiguration, as well as optimizing new applications for reconfiguration on existing commercial devices
FlexTiles: Self adaptive heterogeneous many-core based on Flexible Tiles
FlexTiles is a 3D stacked chip with a many-core layer and a reconfigurable layer. This heterogeneity brings a high level of flexibility in adapting the architecture to the targeted application domain for performance and energy efficiency. A virtualisation layer on top of a kernel hides the heterogeneity and the complexity of the many-core and fine-tunes the mapping of an application at runtime. The virtualisation layer provides self-adaptation capabilities by dynamical relocation of application tasks to software on the many-core or to hardware on the reconfigurable area. This selfadaptation is used to optimise load balancing, power consumption, hot spots and resilience to faulty modules. The emphasis of this project is not the development of the FPGA architecture and its specific run-time reconfigurability. The EXTRA project clearly differs in this topic.
REFLECT: Rendering FPGAs for Multi-core Embedded Computing
REFLECT, funded under the 7th FWP, developed, implemented and evaluated a novel compilation and synthesis approach for FPGA-based platforms. REFLECT relies on aspect-oriented specifications to convey critical domain knowledge to a mapping engine, while preserving the advantages of a higher level imperative programming paradigm in early software development. REFLECT leverages aspectoriented techniques, with a set of transformations to generate an intermediate representation which facilitates the exploration of alternative architectures and run-time adaptive strategies, The effectiveness of the proposed approach is evaluated on applications selected from the domain of audio and video processing, as well as real-time avionics. Unlike EXTRA, REFLECT does not focus on dynamic reconfigurability for commercial FPGA devices, and it does not cover applications for high-performance computing.
CRISP: Cutting edge Reconfigurable ICs for Stream Processing
CRISP, funded under the 7th FWP, is focusing on optimal utilization, efficient programming and dependability of reconfigurable many-core architectures for streaming applications considering their high market potentials. The project addresses the design of more robust and easy-to-use embedded processors that can be used for virtually any stream processing application exploiting optimal utilization, efficient programming and dependability of reconfigurable many-core architectures. The CRISP project envisions a scenario where conventional architectures will be replaced by reconfigurable multicore computing platforms. In such a context, coarse-grained reconfigurable computing will become an important market segment and provides a good opportunity for Europe to have a key position in a market dominated by US companies with fine-grained reconfigurable logic devices. The EXTRA project has a similar objective as CRISP but, in contrast to CRISP, focuses on dynamic reconfigurability. Also, CRISP does not cover applications for high-performance computing.
SARC: Scalable computer ARChitecture
SARC concerns long term research in computer architecture, working on disruptive scalable technology for the next 10-15 years. The SARC architecture is designed to scale from small, embedded systems all the way to large scale, high performance servers. Similarly to EXTRA, SARC used application specific accelerators to obtain maximum performance. Although SARC also targeted HPC systems, it differs from EXTRA as SARC did not specifically target reconfigurable technology. EXTRA will continue research of the relevant parts of the SARC architecture, including the parallel memory technology initially developed for the SARC Vector Accelerator. Finding solutions to the memory wall is an important step towards exascale computing.
MORPHEUS: Multi-purpOse dynamically Reconfigurable Platform for intensive HEterogeneoUS processing
MORPHEUS addresses solutions for embedded computing based on a dynamically reconfigurable platform and tools. The approach is to develop a global solution for a particular modular heterogeneous SoC platform that provides a software-oriented design flow and toolset. These “Soft Hardware” architectures enable better computing density improvements, positioned between general purpose flexible HW and general purpose processors. Runtime reconfiguration is possible with a coprocessor interface and instruction extensions using the TU-Delft Molen approach. Unlike EXTRA, MORPHEUS does not address dynamic reconfigurability for commercial FPGA devices, and it does not cover applications for highperformance computing.
© 2015-2022 EXTRA
The EXTRA project has received funding from the European Union Horizon 2020 Framework Programme (H2020-EU.1.2.2.) under grant agreement number 671653.